This invention relates to improvements directed to implantable pulse generators, such as cardiac pacers, nerve stimulators or a fluid dispenser pump and the like, and will be described with particular reference thereto.
It is known in the art to implant pulse generators within the human body. Such implantable pulse generators include, for example, cardiac pacers, nerve stimulators and fluid dispensing pumps. These pulse generators include a power supply in the form of a battery and a pulse generator circuit all housed in a hermetically sealed housing. The housing may typically take the form of a biocompatible metal case which is sealed so as to be effectively impervious with respect to either gases or liquids. Signals into and out of the circuitry are coupled to the casing by means of feed-through terminals of various types known in the art. An example of such a cardiac pacer may be found in the U.S. patent to A. Ushakoff, U.S. Pat. No. 4,127,134, assigned to the same assignee as the present invention.
From an examination of Ushakoff, supra, it is apparent that the size of the housing is dependent upon that required to house both the battery and the electric circuit, including the pulse generator. The size of the battery depends, to a large extent, upon the anticipated life time, as well as cost factors of the type of battery employed. Improvements have also been made in component packaging and which greatly affect the size of an electric circuit. Thus, the circuitry illustrated in the patent to Ushakoff, supra, shows discrete components as opposed to the integrated circuits or chips as employed in the U.S. patent to A. F. Lesnick, et al., U.S. Pat. No. 4,163,451, also assigned to the assignee herein. The Lesnick patent discloses a microprocessor based pulse generator for use as a cardiac pacer and includes integrated circuits, including active circuits, such as a microprocessor and a random access memory. The use of such integrated circuitry requires less space than discrete components and thus provides a reduction in the size necessary for the circuitry employed in such an implantable pulse generator.
It has been common in the prior art when packaging such electronic circuitry to mount integrated circuits, or IC chips, on a substrate or printed circuit board so that a considerable amount of the surface area thereof was required to mount the various integrated circuits together with interconnections from chip to chip. The recent use of dual in line (DIP) packaging has assisted somewhat in decreasing the size of the contact footprint or square footage area of a substrate used in mounting such chips.
Additional improvements have taken place in electronic packaging that will assist in minimizing the size of an implantable pulse generator. Such improvements include multi-layered ceramic carriers for housing and interconnecting one or more semiconductor integrated circuit chips. An example of such a ceramic carrier is found in the U.S. patent to Gogal, U.S. Pat. No. 4,288,481. This patent discloses a multi-layered ceramic package which is of square shape and is thin in terms of height. A cavity is defined in each of the two major surfaces so as to define a dual cavity chip carrier. Two of the ceramic layers each have a floor surface provided with an enlarged metallized mounting pad for receiving and electrically mounting an integrated circuit chip. Between these two ceramic layers, there is provided metallized patterns, some of which extend to vertical conductive paths or vias which extend to metallized patterns on other ceramic layers and some of the patterns extend to a peripheral edge metallization or castellation. The peripheral or edge castellations extend to a bottom ceramic layer which does not have edge castellations but instead includes vias adjacent its peripheral edges which connect to output contact pads along the bottom surface of the carrier. These contact pads serve as input/output pads so that the carrier may be connected to a motherboard or a substrate.
As noted, the chip carrier disclosed in the Gogal patent, supra, contemplates the use of two ceramic layers intermediate the cavities which individually receive and mount one integrated circuit chip. Additionally, Gogal's structure contemplates that the lowermost layer be void of edge castellations and instead vias extend through the lowermost layer to make contact with an array of input/output contact pads located along the peripheral edges.